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Discussions unrelated to wafer.space or unconnected to IC design. Prefer #general for any IC design or wafer.space related chatter.
Between 2026-08-31 11:59 p.m. and 2026-10-01 12:00 a.m.
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Andrew Wingate 2026-09-01 3:09 p.m.
Interesting talk about some older (80s) architectures that never panned out. I'm excited to see new (potentially old) and novel architectures come online soon!! https://www.youtube.com/watch?v=7Cd4NQu1OG0
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oooooh! queuing that up for a watch, love me some weird architectures!
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(RPI represent 😎 )
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I have been reading though @LukeW's ws run1 submission codebase, and the comments are hilarious. Here is a random selection on setting a false path constraint on a sdff for building a pseudo dff with enable: The Machine Spirit is angry. Brother, get the holy oils (edited)
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8:17 p.m.
( Yes, I read codebases ... I am actually ancient ... This is but a mirage created by a wonderful moisturizer ... ) (edited)
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asic destroyer 2026-09-02 8:18 p.m.
My dual-core keeps getting more and more mature. I’m already getting over 2 CoreMark/MHz out of it, and I’m going to turn it into a quad-core next. Then I think the project is basically done. The only thing that sucks is that I can’t turn it into an ASIC. I need a smaller process node. I really wanted to build an SMP Linux chip. <- @Tim 'mithro' Ansell 🙂 https://x.com/splinedrive/status/2095241420315795911 (edited)
Bro, what the hell did I build? My KianV RISC-V Linux/NetBSD SoC is running Linux 7.2.2 now. I can run desktop apps with an analog clock whose second hand actually keeps perfect time, listen to 256 kbps MP3s, write and compile C/C++ natively with GCC/G++, and even play Doom while listening to MP3…
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Essen
I have been reading though @LukeW's ws run1 submission codebase, and the comments are hilarious. Here is a random selection on setting a false path constraint on a sdff for building a pseudo dff with enable: The Machine Spirit is angry. Brother, get the holy oils (edited)
asic destroyer 2026-09-02 8:33 p.m.
Yeah, that saved my design. I knew nothing about ASICs. Luckily Luke taught me about reset. Pure luck. I really don’t want any shorts. https://github.com/splinedrive/gf180mcu-kianv-rv32ima-sv32/blob/2483ecb9cc00f52dbc2a226fda348d8c139e707c/src/chip_top.sv#L214
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boards arrived! hope they work 😅
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waferspace 1
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Essen
Flex PCB have arrived
Oh in the future I'd probably not skip the back side coverlay over the die. And I'd probably prefer to keep the backside ground plane over the die just not over the pads like that; and in the future don't align the hatching lines or other lines orthogonal to the major bending; i.e., try to keep copper lines from being parallel to the cylinder axis around which the board will be bent. In this case, it'd better be 45° rotated from now.
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Andrew Wingate
Yes, it ended up being one of those, "We can do both, it's the same for us" But then watching them when it was non linear it took a lot more setup and caused other problems that took a bunch of extra time.
Even if they're aligned with the bond wire's axis?
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namibj
Even if they're aligned with the bond wire's axis?
Andrew Wingate 2026-09-04 5:23 p.m.
Alignment with the bond wire has no correlation to anything with setup. Landing locations are just chosen more or less arbitrarily. When the landing locations are linear it seemed like it was easier for them to edit when problems came up, as they could sortof bulk edit. When all the landings were along some arc there was nothing to reference as they're all independent. I hope I'm explaining that right
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Andrew Wingate
Alignment with the bond wire has no correlation to anything with setup. Landing locations are just chosen more or less arbitrarily. When the landing locations are linear it seemed like it was easier for them to edit when problems came up, as they could sortof bulk edit. When all the landings were along some arc there was nothing to reference as they're all independent. I hope I'm explaining that right
Ohhhh
5:28 p.m.
I'd assume then a 2/3 row staggered landing pad geometry with otherwise nice axis aligned grid spacing would not be substantially worse to program and would get much more density than the current single row non-staggered one? Like, the pads on the PCB are much coarser than PCB DRC minimums for copper width/spacing, and those are again coarser than the die side bond pad minimum spacing, and IIRC wedge bonds are a symmetric tool action to attach the wire to the substrate? Just that to end the wire it gets ripped off kinda horizontally in the same direction it came from after attaching to the surface; while ball bonding is very different between start and end action?
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Tim 'mithro' Ansell 2026-09-04 10:45 p.m.
Basically the tool's UI has a thing where you can say I'm placing 10 bonds in a row and then you mark the first and last bond and it places them evenly spaced between them.
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ohhhhh. good/fair
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Tim 'mithro' Ansell 2026-09-05 4:26 a.m.
The whole configuration is manual and entered via a keyboard on a computer.
4:27 a.m.
I'm still very interested in potentially purchasing a wire bonding machine and retrofitting the control system with a RPi that can do all this stuff automatically without having any human do setup.
4:27 a.m.
It could then collect photos of the bonds as they are done as well.
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hmmmm, yeah, I'm surprised it's done all so manually still today, not even loaded from a floppy levels of pre-programming....
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Tim 'mithro' Ansell
It could then collect photos of the bonds as they are done as well.
and presumably bespoke bonding configurations as long as they can get checked by some reasonable DRC gate that keeps the machine from choking /hitting anything in the porcess?
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awwww yeah, mirrored the mezzanine connector pins on my breakout board 🤦
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Doh! Easily done - the original example breakouts were all mirrored but that should be fixed now
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namibj
and presumably bespoke bonding configurations as long as they can get checked by some reasonable DRC gate that keeps the machine from choking /hitting anything in the porcess?
Tim 'mithro' Ansell 2026-09-22 12:07 a.m.
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BreakingTaps
awwww yeah, mirrored the mezzanine connector pins on my breakout board 🤦
Tim 'mithro' Ansell 2026-09-22 12:09 a.m.
This is why I hate symmetry 🙂 -- I've heard multiple horror stories of whole runs of square chips being bonded 90 rotated and stuch.
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ooh that would be rough, at least this is easily fixed
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Tim 'mithro' Ansell
This is why I hate symmetry 🙂 -- I've heard multiple horror stories of whole runs of square chips being bonded 90 rotated and stuch.
offset dicer lines from perfect 90° to force asymmetric dies
3:23 p.m.
s/
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Tim 'mithro' Ansell 2026-09-23 1:55 a.m.
People still tell me that CPUs are boring. That nothing much happens anymore. Let us look at AMD Ryzen 7 processors from 2022 to 2024: the 5800X3D (Zen 3), the 7800X3D (Zen 4) and the 9800X3D (Zen 5). They are comparable 8-core chips with 3D V-Cache. I have written about them before, in How stagnant … Continue reading How did AMD Ryzen get 50%...
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So I'm noodling around http://blog.reprap.org (yes, http) working on an Open Source 3D printed 3D printer that can not only replicate like the original RepRap, but also shrink itself. It's called RepRapMicron. So far we're down to 4um features and repeatable 3-axis positioning to better than a micron. It's all 3D printed, hardware store parts, or from the CNC/3D printer world (use whatever controller you like). Now, Diffraction Limited used a UV fibre source to cure resin, and got a lot of views. RepRapMicron deliberately didn't go down that path because it doesn't scale, but seeing as people seem to like it, here's RepRapMicron doing a 250um wide "Hello, World" anyway. It's remarkably flexible, and made from Nail Art UV resin. (edited)
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5:28 a.m.
Should you want to build one the madness begins here https://github.com/VikOlliver/RepRapMicron/wiki
μRepRap - A 3D printer project designed to work at the micron scale - VikOlliver/RepRapMicron
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Vik Olliver
So I'm noodling around http://blog.reprap.org (yes, http) working on an Open Source 3D printed 3D printer that can not only replicate like the original RepRap, but also shrink itself. It's called RepRapMicron. So far we're down to 4um features and repeatable 3-axis positioning to better than a micron. It's all 3D printed, hardware store parts, or from the CNC/3D printer world (use whatever controller you like). Now, Diffraction Limited used a UV fibre source to cure resin, and got a lot of views. RepRapMicron deliberately didn't go down that path because it doesn't scale, but seeing as people seem to like it, here's RepRapMicron doing a 250um wide "Hello, World" anyway. It's remarkably flexible, and made from Nail Art UV resin. (edited)
It looks like I see an optical fiber
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On Tuesday I gave a little open-silicon back-end tutorial, using LibreLane and the wafer.space template to build a tiny cryptography ASIC, to mostly total beginners at the Practical Open Silicon Workshop (POpSi) https://popsi-workshop.org in Bochum, Germany. Room was full and the tutorial was well received I believe (despite me being a bit disorganized) 😁 Here's the material, in case anyone wants to do similar things in the future: https://github.com/ThorbenMoos/FOSSi_Tutorial. Slides also feature some wafer.space stuff and community contributions.
POpSi — Practical Open Silicon Workshop, September 21–22, 2026, Bochum, Germany.
Hands-on material for a tutorial on the open silicon back-end. - ThorbenMoos/FOSSi_Tutorial
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My TEM visit got cancelled, so I'm going in November
1:10 p.m.
next week Mikhail will be doing some preliminary work, preparing samples
1:10 p.m.
Then do atomic resolution of the gates
Essen started a thread. 2026-09-24 2:16 p.m.
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